This patent application relates in general to integrated circuit device structures and their fabrication. More specifically, the patent application relates to the fabrication and resulting structures of transistors with inner spacers formed using low temperature plasma oxidation.
In some configurations of a nanosheet metal oxide semiconductor field effect transistor (MOSFET), an inner spacer protects the nanosheet channel from the source and drain regions and provides electric isolation and support between the channels. Existing methods of creating an inner spacer can result in poor profile control during etching (such as HF-HCL or reactive ion etch (RIE)). Existing methods of creating an inner spacer can also result in etch-back in the spacer.